1. Field of the Invention
This invention relates to an error correction circuit for correcting errors of data recorded on an information recording medium, and particularly to an error correction circuit for correcting errors of data recorded on an information-writable recording medium using an MFM-RZ encode system (for example, an optical card or the like).
2. Description of Related Art
Various kinds of encode systems such as an NRZ (non-return-to-zero) encode system, an MFM (modified frequency modulation) encode system, an MFM-RZ (modified frequency modulation-return-to-zero) encode system have been known as an encode system for data recording and reproducing operations on and from an information-writable recording medium such as an optical card or the like.
In order to read out data which are recorded on an information recording medium in one of the NRZ encode system, the MFM encode system, the MFM-RZ encode system, etc., the data are input to an error correction circuit to correct errors of the data. If a syndrome represents "0", the error correction would succeed, and thus accurate data could be obtained. On the other hand, if the syndrome represents "1", the error correction would fail.
FIG. 4 is a timing chart showing the encoding of the NRZ encode system, the MFM encode system and the MFM-RZ encode system.
A first (uppermost) stage (a) of FIG. 4 represents a bit sequence of data to be recorded, a second stage (b) of FIG. 4 represents a recording operation of the NRZ encode system for the data, a third stage (c) of FIG. 4 represents a recording operation of the MFM encode system for the data and a fourth (lowermost) stage (d) of FIG. 4 represents a recording operation of the MFM-RZ encode system for the data.
In the NRZ encode system, the polarity of current to be supplied for recording is varied in accordance with the data bit sequence. For example, as shown at the stages (a) and (b) of FIG. 4, the recording current flows forwardly (positively) when a bit to be recorded (hereinafter referred to as "record-target bit") is "1", and on the other hand it flows backwardly (negatively) when the record-target bit is "0". Accordingly, this encode system performs a data recording operation with no period for which the current is equal to zero, thereby improving the recording density.
In the MFM encode system, inversion of magnetization for recording is controlled in accordance with the data bit sequence. For example, as shown at the stages (a) and (c) of FIG. 4, the inversion of magnetization is made when the record-target bit is "1", no inversion of magnetization is made when the record-target bit is "0" and it follows no "0" bit (that is, the bit next to the record-target bit is not "0" bit), and the inversion of magnetization is made when the record-target bit is "0" and it follows at least one "0" bit, that is, at least the bit next to the record-target bit is "0"), whereby the recording density is improved and a self-synchronizing clock signal can be reproduced.
In the MFM-RZ encode system, current supply for recording is controlled in accordance with the rise-up and falling of the bits obtained in the MFM encode system. For example, as shown at the stages (a) and (d) of FIG. 4, current flows for a predetermined period (bit width) at the time when the bits rise up or fall down. Therefore, the reproduction of the self-synchronizing clock signal can be easily performed when the data are read out, and the reproduction of a data read-out timing can be easily performed. In this system, when a data bit is read out at the center of a data period, the data bit is judged to be "1" when the leading edge exists at the center of the data period while the data bit is judged to be "0" when no leading edge exists at the center of the data period.
In the error correction circuit as described above, when the information recording medium is scratched or the like, it may be partially damaged due to the scratch to disturb detection of edges. The disturbance of the detection of edges causes a data loss area where data are continuously lost. FIG. 5 is a timing chart showing a data loss. The stages (a) to (d) are identical to those of FIG. 4, and the bottom stage (e) of FIG. 5 shows a data loss. For example, as shown in the bottom stage (e) of FIG. 5, data are continuously lost in a data loss area, and data error correction cannot be performed in this data loss area by the error correction circuit.
Accordingly, in the error correction circuit as described above, when a data loss area occurs, the error correction is generally performed by setting all data in the data loss area (during a data loss period) to "0", thereby making data decoding possible.
Setting all lost data to "0" as described above can decode all the data without any error if the data were all originally "0's". However, it will not result in error correction if these data were originally "1".
That is, when data are lost due to scratches on the information recording medium, the error rate can be reduced if the original data were `0's`. However, the error rate increases if the original data were "1's". Therefore, the data error rate is dependent on the content of the original data.